1. Field of the Invention
The present invention relates to a transistor structure, and more particularly, to a transistor structure for electrostatic discharge protection.
2. Description of the Prior Art
With the continued miniaturization of integrated circuit (IC) devices, the current trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes, all of which are used in advanced sub-quarter-micron CMOS technologies. All of these processes cause the related CMOS IC products to become more susceptible to electrostatic discharge (ESD) damage. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits of the IC against ESD damage.
Please refer to FIG. 1, which shows a schematic diagram of the electrical circuits having an ESD protection unit. In generally, the main circuit 104 can provide various kinds of functions and can be triggered by supplying signals from the input pad 100. However, in some situation, when an ESD current is formed by a contact between a human body and the contact pad 100 for example, the large ESD current will damage the main circuit 104. Thereafter, an ESD protection device 104 is usually provided in the IC. As long as the ESD current is applied, the ESD protection device 104 is turned on to let the ESD current pass through and further to a grounded site Vss, so the current would not damage the main circuit. 104.
However, current ESD protection device usually has a high triggering voltage and is turned on at a relatively high voltage. It makes the reaction time of the ESD protection device too long and thus reduces the performance of the device.